Derived Metrics 
Utilization rate 
User time divided by wallclock time in percent 
% TLB misses per cycle 
Data TLB misses divided by the number of cycles 
Avg number of loads per TLB miss 

level 1 data cache
load references divided by the number of data
TLB misses 

Total L2 data cache accesses 

Sum
of level 1 load and store misses
Please read the above remark! 

% accesses from L2 per cycle 

Level 1
load and store misses divided
by cycle number
Please read the above remark! 


Level 1 load and store misses
multiplied by the 128 byte cache line size
Please read the above remark! 


The previous line
divided by the wallclock time
For
HPMCOUNT the wallclock time may include
considerable overheads.
Please read the
above remark! 

Load and store operations 

Sum of the L1 data cache load
and store references 

Instructions per load/store 

Number of completed
instructions divided by the above. 

Avg number of loads per load miss 

Counter PM_LD_REF_L1 divided
by counter PM_LD_MISS_L1 

Avg number of store per store miss 

Counter PM_ST_REF_L1 divided
by counter PM_ST_MISS_L1 

Avg number of load/stores per D1 miss 

( PM_LD_REF_L1 +
PM_ST_REF_L1)/( PM_LD_MISS_L1 +
PM_ST_REF_L1) 


Number of level 1 load and store references
not resulting in a level 1 miss. Measured in % relative to
the total level 1 load and store references. 


Completed instructions divided by
wallclock time in 1000000/s 


Completed instructions divided by number of
cycles 
